1. Field of the Invention
The present invention discloses a color sequential timing controlling circuit and both a color sequential display and a method thereof, and more particularly, to a color sequential timing controlling circuit of activating multi-gate lines in cooperation with data arrangement for loading data and both a color sequential and a method thereof.
2. Description of the Prior Art
A color sequential timing controlling circuit is usually equipped on a display applying the color sequential method, for displaying sub-pixels of each of a plurality of pixels on a single full-color frame on a display panel of the display, within an extremely-short time interval in an overlapped manner, so as to take advantages of visual residue in displaying all pixels on the full-color frame.
Please refer to FIG. 1, which is a diagram of a conventional color sequential display 100. As shown in FIG. 1, the color sequential display 100 includes a color sequential timing controlling circuit 110, a data driving unit 120, a scan driving unit 130, a display panel 140, a light emitting diode driving unit 150, a backlight module 160, and two buffers 108 and 112. The display panel 140 determines displayed pixels corresponding to its transistors according to scan lines driven by the scan driving unit 130 and data lines driven by the data driving unit 120. For implementing the color sequential method, the color sequential timing controlling circuit 110 is used for controlling timings of the data driving unit 120 and the scan driving unit 130, so as to load sub-pixels of different colors into the display panel 140 within non-overlapped and extremely-short time intervals. The color sequential timing controlling circuit 100 also controls timings of the light emitting diode driving unit 150 to determine a timing of activating the backlight module 160.
The color sequential timing controlling circuit 110 includes an input buffer 102, an image sorting unit 104, and a drive controlling circuit 106. The input buffer 102 is used for synchronizing a synchronous signal dei, which is inputted from external of the color sequential timing controlling circuit 110, a pixel clock pclk, a plurality of pixels, and a system clock sclk used by the color sequential timing controlling circuit 110. The image sorting unit 104 cooperates with the buffers 108 and 112, so as to output a pixel of a single frame by cooperating with the scan driving unit 130, which merely activates a unique gate line at a time. Sub-pixels within pixels of the frame are also classified according to respective colors, so as to load red sub-pixels, indicated as a capital R on FIG. 1, green sub-pixels, indicated as a capital G on FIG. 1, and blue sub-pixels, indicated as a capital B on FIG. 1, of the frame within non-overlapped and extremely-short time variations with the aid of the buffers 108 and 112, and so as to have the driving controlling unit 106 indirectly control the displaying of the full-color frame on the display panel 140.
For improving data transmission efficiency of the color sequential display 100 shown in FIG. 1, the scan driving unit 130 may be configured to simultaneously activate at least two gate lines. However, as a result, a transmission order between the simultaneously activated gate lines may fail in disorder, and pixels may not be restored correctly after being transmitted, so that the display panel 140 cannot display pixels on the frame correctly as well.